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A quick look back at the conference panel "AI as the Chip Designer: Evolution or Illusion?" that took place at #VLSISoC in Cyprus with Frank representing PULP. See https://t.co/fIgR4YEj8X for details.
And here is Lorenzo who presented his work "Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip" at #VLSISoC in Cyprus. Find the poster and slides here: https://t.co/S1qHxfNCkb https://t.co/LZluFprU60
#VLSISoC is currently underway in Cyprus. Our Bowen is there presenting "Ventaglio: At-the-Roofline Sparse Tensor Contractions on Vector Processors for Transformer Inference". Check out his slides: https://t.co/qBDmo3U6mQ
Interested in a novel approach for verifying processors without a reference model? Today Frank Riese presented our paper "Metamorphic Testing for Processor #Verification: A #RISCV Case Study at the Instruction Level" at #VLSISoC 2021. Full paper here: https://t.co/K7zEtBB3zO
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