#ghdl - Twitter Hashtag

over 1 year ago

Developing one #16APSK Modulator on #FPGA using #PipelineCHDL ! Testbench Datapath: #LFSR -> APSK16 Map -> #CIC Filter -> out Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib ! #dsp #sdr #HDL #ccsds #rf #psk #apsk #modem

DutraCGI's tweet photo. Developing one #16APSK Modulator on #FPGA using #PipelineCHDL !

Testbench Datapath:
#LFSR -> APSK16 Map -> #CIC Filter -> out

Simulation done with #ghdl + #cocotb, data plotted using #numpy and #matplotlib !

#dsp #sdr #HDL #ccsds #rf #psk #apsk #modem https://t.co/Uhvr99PsmM

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Paulo Dutra - PU4THZ @DutraCGI

over 2 years ago

#GMSK #FPGA test with #PipelineC... Simulating with #cocotb and #ghdl

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Patrick Lehmann @PaebbelsLemmi

over 2 years ago

#GHDL v4.0.0 has been released. Get pre-compiled binaries from https://t.co/vKoKJZ2ulV OR compile it your self, following the straight forward instructions at https://t.co/S8aupndgX3 Otherwise trigger your distributions GHDL package maintainer to bump the versions :).

PaebbelsLemmi's tweet photo. #GHDL v4.0.0 has been released. Get pre-compiled binaries from https://t.co/vKoKJZ2ulV OR compile it your self, following the straight forward instructions at https://t.co/S8aupndgX3 Otherwise trigger your distributions GHDL package maintainer to bump the versions :). https://t.co/8jXaWtb7Cu

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Paulo Dutra - PU4THZ @DutraCGI

over 2 years ago

#QAM16 Modulator made with #PipelineC simulation with #GHDL and cocotb! Raised Cosine filter with 0.35 rollof and 4 samples/symbol ! #fpga #qam #sdr #dsp

DutraCGI's tweet photo. #QAM16 Modulator made with #PipelineC simulation with #GHDL and cocotb! Raised Cosine filter with 0.35 rollof and 4 samples/symbol !
#fpga #qam #sdr #dsp https://t.co/iB7lZCZQgQ

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Paulo Dutra - PU4THZ @DutraCGI

over 2 years ago

#PipelineC Raised Cosine FIR Filter simulation with GDHL + cocotb! QAM modulator comming next... #fpga #ghdl #vhdl #rf #dsp #sdr

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University of Global Health Equity

@ughe_org

almost 4 years ago

Earlier this week, the participants in #UGHE Global Health Delivery Leadership Program #GHDL visited Butaro District Hospital, Kirambo & Rwerere Community Health Centers, and Community Health Workers to learn about Rwanda's community health system & community health insurance.

ughe_org's tweet photo. Earlier this week, the participants in #UGHE Global Health Delivery Leadership Program #GHDL visited Butaro District Hospital, Kirambo & Rwerere Community Health Centers, and Community Health Workers to learn about Rwanda's community health system & community health insurance. https://t.co/CrVGWEyarv

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PipelineC (fosstodon.org/@pipelinec) @pipelinec_hdl

almost 4 years ago

A few weekends of work implementing enough #riscv to blink an #fpga LED from C code running on this custom #CPU written in ~"C" 🤓 Sim with @cocotbnews #ghdl and easy debug variables. How much easier could #HDL be? Fun for software and #hardware folks! https://t.co/WXqpnEeJwP

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PipelineC (fosstodon.org/@pipelinec) @pipelinec_hdl

almost 4 years ago

Starting @cocotbnews 🙌 support for PipelineC simulation. Using #GHDL right now for #VHDL. #Modelsim should also be easily possible says docs. #Verilator support I hear is a little unstable with cocotb right now, and also requires a conversion of PipelineC's VHDL to #Verilog...

pipelinec_hdl's tweet photo. Starting @cocotbnews 🙌 support for PipelineC simulation. Using #GHDL right now for #VHDL. #Modelsim should also be easily possible says docs. #Verilator support I hear is a little unstable with cocotb right now, and also requires a conversion of PipelineC's VHDL to #Verilog... https://t.co/8lg76E83h9

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Anton Blanchard @antonblanchard

about 4 years ago

We'll still use the #Yosys and the #GHDL plugin for the FPGA flow, and the ASIC flow uses #Yosys but we need to get at the Verilog to plumb power pins in.

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Anton Blanchard @antonblanchard

about 4 years ago

Another milestone for #GHDL, the Open Source VHDL simulation and synthesis tool - it can synthesize and convert the #Microwatt VHDL source directly to Verilog, without requiring #Yosys. Very useful for #Verilator and Icarus Verilog simulation as well as the #Microwatt ASIC flow.

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Anton Blanchard @antonblanchard

over 4 years ago

A great end to the week. When taping out the #Microwatt processor for an upcoming #sky130 shuttle, we hit some test case failures. Managed to isolate it to a synthesis issue in #GHDL. Submit a bug report, and Tristan Gingold commits a fix within hours. https://t.co/OVZ3FnM1Kf

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Patrick Lehmann @PaebbelsLemmi

over 4 years ago

#GHDL 2.0 got released. It got more #VHDL'08 improvements and fixes for the synthesis feature. It also includes a #Python-API (pyGHDL). GHDL is now going to implement some VHDL'19 enhancements. Lookout for your favorite distributions to bump the version in their package managers.

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Unai @unaimarcor

over 4 years ago

An overview of #GHDL, *the* #opensource toolkit for simulation, synthesis, LSP, documentation,... of #VHDL designs: https://t.co/0YZORJMR9Q #FPGA #Yosys #Verilator #EDAA #Sphinx

unaimarcor's tweet photo. An overview of #GHDL, *the* #opensource toolkit for simulation, synthesis, LSP, documentation,... of #VHDL designs: https://t.co/0YZORJMR9Q
#FPGA #Yosys #Verilator #EDAA #Sphinx https://t.co/qjzHpatr9a

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WaveDrom

@wavedrom

almost 5 years ago

Updated https://t.co/PtRfJkc9XL VCD viewer with basic support for IEEE 1164 9-value logic. Seems to be important for VHDL ecosystem. Here is an example dumped from #GHDL : https://t.co/4YgcETN3uQ

wavedrom's tweet photo. Updated https://t.co/PtRfJkc9XL VCD viewer with basic support for IEEE 1164 9-value logic. Seems to be important for VHDL ecosystem. Here is an example dumped from #GHDL : https://t.co/4YgcETN3uQ https://t.co/dczLTf8wph

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Unai @unaimarcor

about 5 years ago

@BrunoLevy01 @ShawnHymel Many users stick to <2006 languages (Verilog 2005 and VHDL 1993 or 2000) because of limited support or price in vendor tools. However, that is not an issue any more, because #GHDL (FLOSS) supports VHDL 2008 and can output a VHDL 1993 or Verilog netlist for synthesis purposes.

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Unai @unaimarcor

about 5 years ago

@ShawnHymel More about VHDL: - Sites: https://t.co/CrulQjazPr - Books: https://t.co/lulDESU9VM - Projects for synthesis: https://t.co/hzY1jKoVVQ - Formal verification (#PSL, #GHDL, #Yosys and #SymbiYosys): https://t.co/eWRn8zah2g and https://t.co/XSRwdgTXnp

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Unai @unaimarcor

about 5 years ago

Support for synthesis targeting #ECP5 #FPGA devices (through #ghdl+#yosys+#nextpnr+#prjtrellis) was added to #NEORV32. An example for @GregDavill's #OrangeCrab is available: make -C setups/examples BOARD=OrangeCrab MinimalBoot https://t.co/jVbpasE3uW

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