TerosTech

Develop hardware, take advantage of software tools. TerosHDL

[TerosTech @terostech]

TerosHDL (Teros Technology) v2.0.3 includes full support for VSG (VHDL Style Guide):

- Create your own style rules for VHDL: https://t.co/nSVr3SNkp4

- TerosHDL will show the rule violations in your code and quick fixes: https://t.co/Iel1N59Txp

#vhdl #verilog #systemverilog

[Olof Kindgren @OlofKindgren]

Nice! EDAM loading seems to work fine. Would be awesome to find a way to use core description files directly as project files as well in the future

[Olof Kindgren @OlofKindgren]

Just installed VS code with the @terostech TerosHDL extension. First time ever writing Verilog (or pretty much any code for the past 20 years) outside of Emacs and first time using VS code. Damn, this feels weird but I look forward to see how it feels once I have adjusted

[TerosTech @terostech]

- Verilog/VHDL State machine viewer & designer: https://t.co/9W4zRRhVjl
- Improved documentation generator: https://t.co/gWWQY2K17u
- Verilog/SV schematic viewer (beta): https://t.co/tM2iqzRVxb
- Project manager (Only Vunit): https://t.co/3ctsGD0wKF

[TerosTech @terostech]

TerosHDL VSCode jumps to v0.1.0 after some weeks of heavy development!
#eda #fpga #TerosHDL #IDE #HDL #Vunit

Some of the long waited new features included in v0.1.0:
- A proper documentation web page: https://t.co/8L9IgmKSRk

[TerosTech @terostech]

We are pleased to announce our participation in
@OSHWDem 2020!

TerosHDL's talk will be at 10:00 am on Saturday (November 7). We will talk about the latest version (v0.0.6) of the VSCode plugin.
We are waiting for you all!!

#FPGA #verilog #vhdl #ide #hdl #vscode

[TerosTech @terostech]

We are pleased to announce our participation in @esLibre_ 2020!

TerosHDL's talk will be at 4:00 pm on Saturday (September 19) on "Pista II". We will talk about the latest version of the VSCode plugin.
We are waiting for you all !!

https://t.co/SclE34bcmQ

[TerosTech @terostech]

Documentation:

https://t.co/GnRjpVj7Q3

Donwload:

https://t.co/IhwORmI6dZ

[TerosTech @terostech]

Finally we have a beta version of TerosHDL 0.0.4 including all the editor features in VSCode.

For all OS. Verilog & VHDL

- Go to definition
- Hover
- Template generator
- Documenter
- Linters
- Style checking
- Code formatting
- Dependencies viewer

#verilog #vhdl #teroshdl

[TerosTech @terostech]

Dependencies viewer in TerosHDL 2.0 by VUnit

#VUnit #verilog #vhdl #eda #hdl #teroshdl #verilator #ghdl

[TerosTech @terostech]

We continue to develop new features in TerosHDL 2.0
Preview documentation instantly looks really nice!
#teroshdl #eda #hdl #verilog #vhdl

[TerosTech @terostech]

We are pleased to announce our participation in FOSDEM 2020!

TerosHDL talk will be at 13:15 on Sunday (February 2) at Free Tools and Editors devroom.
We wait for you all!!

https://t.co/rOFhT4xGlf

[TerosTech @terostech]

@OlofKindgren @VUnitFramework Thanks for sharing @OlofKindgren We are going to check out the docs! It will help us a lot for the next version.

[TerosTech @terostech]

We continue working on TerosHDL 2.0.0! We have already added continuous integration test with Github Actions #fpga #vhdl #verilog #eda

[Flo @FlorianWoh]

#ORConf in #Bordauxe ist in full swing
Now #TerosHDL presenting
@FossiFoundation #riscv @openhwgroup

[TerosTech @terostech]

Talking about the new features of Teros HDL #ORConf #Vunit #cocotb #edalize #eda #vhdl #verilog #verilator

[TerosTech @terostech]

On the way to #ORConf!!

[TerosTech @terostech]

Working with Coco Tb is already possible in Teros HDL!! #cocotb #vhdl #eda #teroshdl

[TerosTech @terostech]

The finishing touches are ready!! TerosHDL 2.0 #Vunit #verilator #cocotb #ghdl #verilog #vhdl #eda

[TerosTech @terostech]

The schedule for ORConf is now available! https://t.co/fdkYz91x2u We wait for you all on saturday at 12:20 @FossiFoundation.
Looking forward to talk about the latest features of Teros HDL!! #verilator #cocotb #ghdl #verilog #vhdl #eda #edalize #vunit #verilog #ORConf