#edalize - Twitter Hashtag

almost 5 years ago

#openFPGALoader is now in v0.5.0 🎉 - spi bridge for @IntelFPGA (cyclone IV & V) and @XilinxInc spartan6 - spi bridge is build with @OlofKindgren #edalize - windows and Linux bin build at each new commit or release - #FOMU support

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Olof Kindgren @OlofKindgren

almost 5 years ago

@kamcmahon @risc_v Easy! Just piggyback on some other hot hashtags. Like this: #riscvsummit #awardwinning #serv #swervolf #fusesoc #edalize #olof

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PDVL @PDVLcc

over 5 years ago

@OlofKindgren @timonsku Awesome, reminds me of the time 20 years ago, when we automatically converted VHDL/Verilog to cycle accurate C models of the design and timing accurate JAVA testbenches, so IP providers can offer black model simulations. Maybe now it's time for that business model #edalize.

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Sylvain Lefebvre @sylefeb

over 5 years ago

Silice master update! - new build system (with #edalize!) - generic interfaces (see sdram controller) - partial table/bram initialization - support for new boards Thanks to @robng15, @GwenhaelG, @OlofKindgren, @rsnous for contributions, suggestions and bug chasing.

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Sylvain Lefebvre @sylefeb

over 5 years ago

@gojimmypi The wip branch contains a new build system that makes it very easy to target different FPGAs through @OlofKindgren #edalize . Simply type 'make icebreaker' or 'make ulx3s' from command line. https://t.co/Hh6mKNhnyI

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GwenhaelGoavec

@GwenhaelG

almost 6 years ago

@BluffJe @ico_TC @enjoy_digital For synthesis, #yosys work well (tested with spartan6 and spartan7 see: https://t.co/XEcKX6f7G5) and vivado backend in @OlofKindgren #edalize support #yosys as alternate tool.

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TerosTech @terostech

almost 7 years ago

Talking about the new features of Teros HDL #ORConf #Vunit #cocotb #edalize #eda #vhdl #verilog #verilator

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TerosTech @terostech

almost 7 years ago

The schedule for ORConf is now available! https://t.co/fdkYz91x2u We wait for you all on saturday at 12:20 @FossiFoundation. Looking forward to talk about the latest features of Teros HDL!! #verilator #cocotb #ghdl #verilog #vhdl #eda #edalize #vunit #verilog #ORConf

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