Top Tweets for #fusesoc
Watch talks from members on collaborative #opensource projects including Open Se Cura, #Caliptra RoT, #Chipyard, #UVM testbenches in #Verilator & using #FuseSoC w/ VeeRwolf: https://t.co/D8eDWprmvF @linuxfoundation @risc_v @Google @antmicro @verisilicon @UCBerkeley @OlofKindgren
@OlofKindgren @CHIPSAlliance @FossiFoundation @antmicro Cool, @OlofKindgren speaking about FuseSoC package manager which is also used by #OpenHW #Chipsallianze and many others, a package manager for IP
#semiconductor #fusesoc @FossiFoundation
During the Technology Update, we'll explore #FuseSoC, a package manager for IP cores covering a wide range of work flows. Learn about the basics of FuseSoC using VeeRwolf and how you can adopt it in your chip design: https://t.co/N7zHq9yHVd @OlofKindgren @risc_v @linuxfoundation
Made @esse_nao_pode #huedeon GPU + #riscado (RISC-V) run on Kintex 7 from #qmtech! I also added @OlofKindgren #fusesoc because I didnt want to deal with 200 diferent tools 😂
https://t.co/6VEw39mtin
Sunday afternoon choices…
- CAM to CNC mill around these too-tall tantalums under the Gameslab heat spreader
- Finish my award winning #fusesoc generator core for Zynq PL so I don’t have to open Vivado’s GUI
- Port RBoy https://t.co/gEUqe1dOkl
- Port DOOM https://t.co/jl9jdMnmXP
@kamcmahon @risc_v Easy! Just piggyback on some other hot hashtags. Like this:
#riscvsummit #awardwinning #serv #swervolf #fusesoc #edalize #olof
Another board (STLV7325) added to the amazing blinky project! Pls increment the counter @OlofKindgren
🔂
PR: https://t.co/F0hGMCczy0
https://t.co/oDQITR6xnR
#fusesoc #blinky
Just added support to @mithro and @xobs Fomu to Fusesoc blinky.. the project that is "One blink to rule them all"! Thanks for the insane fase merge @OlofKindgren.
https://t.co/b68U5CInCZ
#FPGA #FuseSoc
Wrote a https://t.co/VRKNYfXEKP about #fusesoc which I contributed at porting cores to two new #FPGA boards (Arrow #Sockit an Arrow #Deca) @OlofKindgren https://t.co/IkfGZn84PS
Just discovered #corescore by @OlofKindgren and have tried it with #CYC1000 (#60) and SoCKit (#284) #FPGA boards. Here is the code if you want to test your board https://t.co/3KdC7KdgQ1 #SERV @risc_v. #fusesoc rocks by the way ;)
@OlofKindgren It just means someone needs to package a nice SoC around it now (#fusesoc or #litex ?)
Thank you for SERV! Awesome job making nice old C available to any fpga owner out there!
Check out @antmicro’s blog post to read about the free, open SweRV cores and how to get started using them.
https://t.co/75sXo80xWX #Verilator @renodeio #FuseSoC #LiteX @symbiflow
#SweRV is a family of production-grade @RISC_V cores from @westerndigital under the governance of @CHIPSAlliance, with a range of MCU options. Read about our work with #opensource tools for SweRV: https://t.co/fKFrrkYFys #Verilator @renodeio #FuseSoC #LiteX @symbiflow
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