@FrankfurtZack Dafür wurde mittels Änderung der Nasdaq Regeln vorgesorgt. SpaceX landet nach 15 Tagen per fast-track mit 3x multiplier im Index: https://t.co/16bXTnS6Cl
Damit sind sie nicht auf die Fans angewiesen, sondern die Indexgebunden Fonds werden gezwungen mit einzusteigen.
@minut_e @austriancoder The 8MP GPU has significantly less fillrate, due to having only a single pixel pipe. For comparison: fillrate is lower than the GC3000 on i.MX6QP even when the GPU is clocked at 1GHz.
@minut_e @linux4kix @arvidep This periodic signal is the https://t.co/cpnOnRQ4YW stage of the PCIe LTSSM, where the transmitter tries to find out if there is a load connected on the other end of the link. If the lanes don't detect a receiver, they go back into detect.quiet state.
@marcan42@loekf AMD calls this "DRAM stutter mode" IIRC. I don't know much about the Apple GPU, but if it renders into a tiled format and you want to resolve this in the scanout you need tilesize-Y * dispresolution-X SRAM space to do a continuous fetch from DRAM.
@mntmn@llandwerlin@jekstrand_@timonsku@furan Etnaviv currently ends up being CPU bound in some of the glmark2 benchmarks and we actually regressed in this area with newer Mesa versions. I'm currently working to rectify this. Hope we don't get beaten as bad anymore when I'm done.
@mjg59 The way it works is that one device explicitly publishes p2p memory and another can map that via pci_p2pdma_map_sg_attrs. Whether the transaction goes through the host bridge or a downstream switch depends on ACS policy, but shouldn't bother you in a driver.
@chainq@mntmn Reality streams crossing for me. Being mightily impressed by .the .product was one of the motivations for me to get into low-level graphics programming back in the day, which ultimately lead to me being part of the team building the graphics driver powering the MNT Reform.
@pdp7@risc_v The 1:1 hart:core mapping implied here is not really true. A SMT core will have have multiple harts, but with some imagination you could also run a single hart on resources of multiple cores at the same time.
@pdp7 Ryzen 2700 at 65W TDP, as that one is easy and cheap to cool. Fast enough to not drive you crazy when cross-compiling Qt5 or Chromium, but almost noiseless, so able to keep in the same room. Current equivalent would be Ryzen 3700X, I think.
@mntmn What a beauty! Now I want one again, after months of trying to wrestle down my inner hardware hoarder. Is payment in https://t.co/5lw6jTvTra patches accepted?
@pdp7@austriancoder Yep, just add the DT node with register space and clocks. Kernel driver should be able to figure out everything else from the feature registers. Mesa may need some patches to know about display controller.
@pdp7#etnaviv on freenode and etnaviv ML on freedesktop. I doubt that anyone can tell you more than "might work". As with all this RE stuff we can just look at the feature bits and tell you if we've seen them already. If yes, chances are good that things will work, but no guarantees.
@pdp7 While I'm not aware of any real world-experience with this GPU core, the feature bits looks like it has less features than the GC7000L and nothing scary. So I would expect that etnaviv either runs out-of-the-box or with minimal changes.
@mntmn@Lynntendo64 RYF is strange anyways. Their firmware ROM rule incentivises companies to put closed source firmware in read-only locations to make is OK for RYF. IMHO loading firmware from user accessible location, giving me the option to tinker with the blob, respects my freedom a lot more.
So this is the wildest debugging technique I've used recently: OpenGL, being a stateful API, has a bunch of relatively generic entry points that can set states nowhere near where you use them. Decades of OpenGL wisdom says "cache all the state you can and don't set it twice."