Starting the new year with a fun new project: going to build a startup, from scratch, in public, in 80 days β±π . https://t.co/U63IvynhEF #80daystartup#buildinpublic
@cmuratori Personally, I'd say it's less about open vs closed, but more about whether there is an actually _documented_ API at some "reasonable" level of abstraction.
@suarezvictor Nice. The emulator should work, though it is very slow. IIRC it ran the final FPGA craft design at ~10khz on my PC. So alternatively you could run Wyre first to compile to Verilog, and then use a tool like Verilator.
@suarezvictor Yeah that would be cool. Might even be able to pair the GPU module with another CPU (RISC-V?). To be clear, I'm working on other projects so I won't be able to help out or accept PRs, you're on your own. But absolutely feel free to fork the project and go for it :)
@cmuratori And there are caveats regarding docs (incomplete, sadly), HW tooling and HW languages. So not a perfect platform by any means, though once you get past these hurdles the result can be pretty awesome.
@cmuratori iCEBreaker FPGA board. Minimal feature set, so basically only does what you tell it to and nothing else, which is great. But very underpowered, can run HW designs up to ~40Mhz and has just 128kb (no typo). (1/2)
@suarezvictor I'd start with the FPGA_craft GPU module and "unhack" it to be more general, could be pretty fun. Keep in mind though that the GPU is quite limited: it can only render axis aligned voxel cubes. In the video, it's technically not the cube that's spinning, it's the camera ;)
@suarezvictor Thanks Victor, unfortunately I don't, in retrospect I probably should have used more frequent source control checkins during development (I'm not sure if this version was kept anywhere). If I wanted to recreate this now, (1/2)
@PatrickPelgrim1 @BrunoLevy01 Agreed. For this design it probably wouldn't make a big difference due to all the other components, but if we wanted to reuse the CPU in other projects that could be useful.
@_ediri Thanks! It should be possible to port the project to another FPGA. The target FPGA likely has (way) more LUTs than the iCE40 that I'm using, so you probably wouldn't have to worry about LUT usage. Though it will require remapping of the iCE40 specific IP blocks.
@PatrickPelgrim1 @BrunoLevy01 It does not. Though, currently, the CPU spends roughly 80% of its time micromanaging the GPU (mostly waiting), so interrupt support would be a nice addition!
@ThomasPototsch1 @trc_wm @Claude1079 Fair enough, definitely not impossible though ;). And I hope it will be a cool thing for people to check out and maybe learn from.
@d1sasm I've decided to wrap up the project here for myself, but it's definitely a cool idea though :). The code is open source, so if anyone is interested they should absolutely feel free to go for it!
@ThomasPototsch1@Claude1079 Thanks! Mostly to allow for a smaller size firmware and to learn about CPU/instruction set design which was fun :). Though there are definitely pros/cons to this approach.