Oski Technology is hosting the next Decoding Formal Club meeting on April 23rd. Featuring talks by Vikas Minglani of Fungible, Inc., Jing GAO of Qualcomm and author Erik Seligman.
For more details and registration see: https://t.co/DC9eSLbFMY
Oski Technology is hosting the next Decoding Formal Club meeting on September 25th.
Featuring talks by @AMD, @Broadcom and Vigyan Singhal, Founder and Chief Oski.
Read more and register here: https://t.co/nQndf1FVHB
“When you architect the design or make decisions about the blocks and microarchitecture you must understand concurrency versus sequentiality as a first-class decision point”, said Vigyan Singhal of @OskiTech. Read more: https://t.co/iN6TnaeNa2
Can the IC verification challenge be solved by parallelization? Experts from Altair Engineering, @Cadence, @mentor_graphics, @OneSpinSolution, @OskiTech and @ANSYS discuss the answers with @SemiEngineering. https://t.co/jwjqgPdLnG
Simulation-Resistant Superbugs - A Central Theme at DAC. Combating these superbugs is the mission @OskiTech. Case studies by @CaviumInc, @Cisco, @nvidia, and @Qualcomm, Superbug Risk Assessments, Executive Summit to discuss epidemic took place. Read more https://t.co/UrgIm3mQBF
@CaviumInc case study on how they used @OskiTech Formal to combat simulation-resistant superbugs in their Software Configurable Silicon for SDN given to a packed audience in Oski booth at DAC. Missed DAC? Watch the full video version at https://t.co/aMWVLvOabI
#formalverification
The #Wolper Method https://t.co/rsdKKeR0NT
"If you read around topics in advanced formal #verification you’re likely to run into something called Wolper coloring, or what Vigyan Singhal calls the Wolper method."
Read about this on #SemiWiki@OskiTech
Thank you, Kamal from @OskiTech for showing us how simulation-resistant superbugs are a real problem in today's designs and how Oski Formal can find those bugs early, avoiding critical bug escapes and achieving verification sign-off https://t.co/xb0nHYKoCR
@OskiTech to provide Simulation-Resistant Superbug Assessment at DAC. We'll rank orders design blocks by superbug risk so you can employ the right verification strategy to achieve predictable, efficient, and confident sign-off. Book at https://t.co/xVB1zunTtc #formalverification
@CaviumInc, @Cisco, and @Qualcomm share how they eradicated simulation-resistant superbugs using deep application-specific formal verification methodologies from @OskiTech at this year's @55thDAC. Don't miss their secrets. Sign up for these sessions at https://t.co/75oNsc9haA
Simulation-Resistant Superbugs Are Here. Time to Rethink Your Verification Strategy. Craig Shirley @OskiTech delivers insights on how these new class of bugs affect an array of domains and how simulation and emulation are not be enough to combat them - https://t.co/8uyLbtNNbL
Does Power Verification Work? Read @brian_esl article on @SemiEngineering to find out. Roger Sabbagh, VP of Application Engineering @OskiTech shares his thoughts. https://t.co/M7az8XSl5r
Kamal Sekhon from @OskiTech presents at SNUG a 3-step guide to Architectural Formal Verification to address complex system-level challenges https://t.co/OWmdJmcosz
Formal Signoff – a #Cisco Perspective https://t.co/YadmcfMlht
"The second segment of @OskiTech most recent 'Decoding Formal' event was a talk by Anatoli Sokhatski...on training and methodology development for a structured and scalable approach to formal verification..."
#SemiWiki
Anatoli Sokhatski from @Cisco relays his team's experience with formal sign-off and how @OskiTech Formal expertise and methodology were key to their success. Story on SemiWiki https://t.co/1LNQjTlVhb
Video: https://t.co/wML8G3VD8h
JasperGold Under the Microscope - Kamal Sekhon of @OskiTech delivers @Cadence Boston CDN Live Trip Report on @ADI_News use for static timing analysis https://t.co/2FlhIW74oz and @Teradyneinc use of for basic formal https://t.co/3rsU8QpXbw