Osama Khan

A new life awaits you in the off-world colonies! A chance to begin again in a golden land of opportunity and adventure!

[Osama Khan @osmkhn]

I think Elon’s Terafab will mark the return of Jim Keller with his Atomic Semi work

[Osama Khan @osmkhn]

@elonmusk Geth. This is how we get Geth. Please go consult the 3 primary historical sources for more on this and how it turns out. (You can skip the fourth primary historical source)

[james hawkins @james406]

PARENTS: please check your kid's candy this halloween - i just found a 12-month enterprise salesforce contract for 15 seats with auto-renewal and a $50,000 early breakup fee inside this snickers bar

[Clark Tang @_clarktang]

Wonder what 2.5D advanced packaging / CoWoS looks like? ASE showed off a super cool model in Taiwan that demonstrates the various components of an advanced package "XPU / GPU" and how it is bound together by CoWoS (Chip on wafer on substrate)

Center piece is the XPU logic die which does the calculations - (largest volumes made by $NVDA and $AVGO)

The piece surrounding it with many layers is HBM - high bandwidth memory (made by SK Hynix, $MU, and Samsung)

They are packaged together with microbumps onto the copper colored RDL.

Underneath, silver colored is the silicon interposer.

Finally they are placed onto the substrate itself.

This complex process of advanced packaging is done to create a combined chip that is able to access different capabilities at a very fast rate (in the case of the XPU, it's to access the high bandwidth memory faster).

Note you can see that the shoreline of the XPU (aka closest to the logic die for fastest I/O) is dominated by HBM. Often times AI workloads are memory bandwidth constrained, aka the constraint on the system is how fast the XPU can read and write their calculations to memory

Advanced packaging is here to stay and continue to grow as techniques will expand past just the leading edge AI accelerators like GPUs and XPUs. In fact, $TSM on their last earnings call doubled their view of their Foundry TAM from $115B to $250B when including packaging, testing, and mass making!

TSMC, ASE, Amkor are the leaders today in advanced packaging. In fact, ASE who presented this model invented this 2.5D - what TSMC calls CoWoS in 2014 alongside AMD.

Fascinating times for the semis industry

[Osama Khan @osmkhn]

@Behind_Pics Is that Trent Reznor ?

[Osama Khan @osmkhn]

@sohailabid Most fresh grads I interview these days don’t even know what a BIOS is.

[Osama Khan @osmkhn]

@Tesla User supplied audio files? Those codecs better be written in Rust and fuzzed to oblivion because this is going to be a giant bullseye for exploits !

[Osama Khan @osmkhn]

@jessfraz Noice

[Tech Fund @techfund1]

Some interesting analysis from TechInsights on SMIC's N+2 node (processor in Huawei's latest phone):

One of our salespeople in Asia was able to procure a Huawei Mate Pro 60 and hand carried it back to the lab in Ottawa.

When we analyzed the previous N+1 device we found pitches in line with TSMC’s 10nm process but also more advanced features like single diffusion break and 6 track cells not seen until TSMC 7/7+ processes. The overall density of the dense logic on N+1 was slightly less than TSMC 7nm but close and we called N+1 a 7nm class device.

TSMC’s original 7nm process was all done with optical multipatterning, the pitches were all achievable with double patterning except the fin pitch that required quadruple patterning.

The N+2 Contacted Poly Pitch (CPP) and Metal 2 Pitches (M2P) are both tighter than N+1 but not as tight as TSMC 7nm, CPP in particular is relaxed from TSMC 7nm. CPP is made up of gate length (Lg), contact width (Wc) and gate to contact spacer thickness (Tsp). Lg is limited by leakage, Wc by parasitic resistance and Tsp by parasite capacitance. This indicates to me that SMIC is still struggling to achieve low leakage and low parasitic resistance and capacitance, M2P is much closer to TSMC 7nm. The overall high density logic transistor density for N+2 is intermediate between TSMC 7nm and 7nm+ making it a solid 7nm process. There is even some room to further shrink the pitches with double patterning to achieve something along the lines of TSMC 6nm densities in a future process (N+3?).

N+2 is an incremental improvement over N+1 moving from a borderline 7nm process to a solid 7nm process. This process is still within the limits of what optical double patterning can achieve and even has some room for additional shrinks.

Full article:
https://t.co/tdTatNdy5X

Comparing the Mate60 chip (CN) to the previous one (TW):

[Patrick Chovanec @prchovanec]

A lot of things in the world become clearer when you realize that people can hold contradictory ideas in their heads at the same time, and not necessarily see the need to resolve them.

[Karl Sharro @KarlreMarks]

This eating malarky is totally pointless. You eat then you're hungry again a few hours later and have to eat again and it keeps going on.

[Osama Khan @osmkhn]

@thommcg1980 County Clare remains a charging desert as usual.

[Matthew Green @matthew_d_green]

Computer security would be about 80% solved if we just deprecated every technology shown in this graphic.

[Matthew Green @matthew_d_green]

Look what I just found on page 864 of the FY’24 National Defense Authorization Act. https://t.co/eQ2zGKCLmM

[Osama Khan @osmkhn]

@mahobili Very therapeutic. Thanks.

[Massimo @Rainmaker1973]

The Fourier Transform explained in one sentence

[source, Stuart Riffle: https://t.co/rszYJYkzUC]

[Osama Khan @osmkhn]

@dahmad97 @BrovaPova @Profitpk Very disingenuous. This is a long term lease. Claiming sale in the first tweet to get engagement and then adding a disclaimer below. This was intentional.

[Whole Mars Catalog @wholemars]

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