Roy Cohen

[Roy Cohen @0xbadcaffe]

@straceX you can use pahole tool in Linux to find these “holes” in binaries if they were compiled with debug info

[Roy Cohen @0xbadcaffe]

@splinedrive Try with make -j$(nproc) so it will 🔥

[Roy Cohen @0xbadcaffe]

@circuitofrito1 @splinedrive +1 for the usb hub model tx.

[Roy Cohen @0xbadcaffe]

Does anyone have experience with the STLINK-V3PWR?
https://t.co/A3T9pnfJ9I

[Roy Cohen @0xbadcaffe]

@ATaylorFPGA Nice.
These US+ evals have LOTS of peripherals and power configuration, I guess implementing the entire reg. map ICD could be plenty of work but rewarding.

[Roy Cohen @0xbadcaffe]

@FPGA_Zealot What’s the pcie riser you’re using?

[Roy Cohen @0xbadcaffe]

@suarezvictor @ultraembedded @enjoy_digital That’s the Arty A7?

[Roy Cohen @0xbadcaffe]

@splinedrive Looks interesting!
This is my Tanenbaum copy

[Roy Cohen @0xbadcaffe]

@ATaylorFPGA zcu102 is the mpsoc king

[Marcelo Samsoniuk @samsoniuk]

thanks, Vivado! 😅

[Roy Cohen @0xbadcaffe]

@system76 STOP CAT ABUSE!

grep "foo" "bar.txt"

Not

cat "bar.txt" | grep "foo"

[Roy Cohen @0xbadcaffe]

@RealTimeKodi I see clk and data no chip select so could be i2c

[Roy Cohen @0xbadcaffe]

@ATaylorFPGA Dark mode finally 🤩 can’t wait for Vivado Code 😉

[Roy Cohen @0xbadcaffe]

@splinedrive Which eval board is that?

[Roy Cohen @0xbadcaffe]

@arturo182 @TransmutableCo Shut up and take my money lol

[Roy Cohen @0xbadcaffe]

The Bible second edition

[Roy Cohen @0xbadcaffe]

@DigilentInc Arty-S7

[Roy Cohen @0xbadcaffe]

@ATaylorFPGA 2