Ivan

Almost Computer Engineer @FCEFyN_UNC.

I like low level stuff: RTL, comp arch, compilers, OS dev

[HardMatrix @hardmatrixdev]

Digital design is still too locked behind licenses and closed tools.

Modern open-source flows are worth another look.

We wrote about the hardware design stack we use:

https://t.co/EIJlWzJ6yT

#DigitalDesign #OpenSource #ASIC #FPGA

[HardMatrix @hardmatrixdev]

You're probably overcomplicating your testbench.

Model the behavior, enforce standard interfaces, and use lightweight verification libraries. That's it. And it scales.

Check our latest blogpost:
https://t.co/TQNuQy9JAH

#FPGA #DigitalDesign #ASIC #Verification

[HardMatrix @hardmatrixdev]

CRC, Reed-Solomon encoding, PRBS all use the same serial feedback loop underneath.

The trick to running k inputs per cycle isn't pipelining, it's matrix exponentiation.

Check our latest blogpost:

https://t.co/EcjpE1KHI2

#FPGA #DigitalDesign #ASIC

[Ivan @IvanVig]

I’m glad to share that we started @hardmatrixdev

I get to do it alongside people who are not only friends, but also great professionals and engineers I deeply admire

More coming soon

[HardMatrix @hardmatrixdev]

We started HardMatrix to build serious digital hardware: IP cores, ASIC/FPGA systems, and to help create a more open and capable semiconductor ecosystem.

Small team. Deep technical focus. Long-term mission.

[Ivan @IvanVig]

@JustinLDallas you do both. Your testbenches should always check de results so you build a regression suit. When the tests don't pass, you open the waveform and analyze the signals to debug the problem

[Ivan @IvanVig]

@redixhumayun @kai_fall @RazorSharpFang Is not obvious at all, in hardware is really common to use msb first reprentation so a concatenated with b could easily be interpreted as [a, b] where the bits of a are in the high part

[Ivan @IvanVig]

@flybondioficial me cancelan el vuelo a menos de 24hs de volar y no me atienden por ningún medio para reprogramar, que se supone que debo hacer??

[LaurieWired @lauriewired]

OS internals books are wild...

[Ivan @IvanVig]

preview of a Sphinx autodoc extension for Verilog that Im working on

[Ivan @IvanVig]

@splinedrive I'm glad you liked it! Sutherland has a couple of nice papers, I would also recommend the one about X propagation and the one about assertions embedded in the design.

[Ivan @IvanVig]

@splinedrive This is a great pdf about useful synthesizable SV features https://t.co/lgvsoD89Vg

[Ivan @IvanVig]

@OlofKindgren I've been using fusesoc generators to integrate IP cores from Xilinx to my desings and to run tests with svunit, its a really useful feature

[Ivan @IvanVig]

@mikeev @OlofKindgren Haven't tried it yet, but I really liked the concept of generators in Chisel, where you have this clear boundary between a more powerful abstract part that is executed in compilation time and a more constrained part that represents actual hardware

[Ivan @IvanVig]

@mikeev @OlofKindgren Also the language have some limitations, functions are more ergonomic than modules for small hw, but cant use them since arguments need a fixed width, you can wrap them as static methods of parameterized abstract classes but that has poor tool support and its rather hacky.

[Ivan @IvanVig]

Holy shit FuseSoC is such an amazing tool, glad to see people pushing rtl design into the right direction

[Pulp Librarian @PulpLibrarian]

This is the future they took from us.

[cocotb @cocotbnews]

Let's start with an introduction. World: this is the new cocotb Twitter account. @cocotbnews: this is the Twitter world.
Hello everyone! Just to let you know: I now also have a brand new logo and a website at https://t.co/kodSswjxEv. Thanks to Lena Alm for the logo design!

[Oliver Cameron @olivercameron]

Here's @ylecun in 1993(!) demoing LeNet-1.

This was the world's first convolutional neural network for handwriting recognition. Today—29 years later—this same approach powers the majority of computer vision.

Such a historical moment, and breakthrough for machine learning.