Don’t worry, If you haven’t registered for our next episode of #OpenHWTV, you’re not too late! Register now to save your spot & join in on the conversation with @rickoco, @be4web, @gmax79, and @DaveStratman from @Cadence!
Registration Link: https://t.co/3Gx2j4Q1t9
#OpenHWGroup
We’re counting the days until our next episode of OpenHW TV, April 21 at 8am PDT! Listen in as we discuss, “What’s Behind the Infrastructure of the CORE-V Family,” & craft your questions to ask during our live Q&A https://t.co/3Gx2j4Q1t9
@rickoco@be4web@gmax79#opensource
Learn about the artificial intelligence angle of the OpenHW Group CORE-V family. Check out S03/E02 of OpenHW TV Driving AI/ML Innovation with CORE-V, Open-Source RISC-V Based Processors https://t.co/tJXYAcOvqE
#OpensourceHW#opensource
Don’t miss the Open Source HW Panel on Industrial Concerns at DATE -- Friday, March 18th. Where the discussion will go beyond the buzz & discuss opportunities, roadblocks & what the future holds. https://t.co/l3xHSm4EIJ
@rickoco#opensourceHW#opensource @DateConference
Join us today at 8 AM PDT for Episode 3, OpenHW TV Seeding the Next Generation of Innovators with Open-source RISC-V Processors.
Register: https://t.co/EL8rlHh9pP
@rickoco@ETH_en@risc_v
Attending virtual DATE this week? Join us at the Open Source HW Panel on Industrial Concerns. Where the discussion will go beyond the buzz & discuss opportunities, roadblocks & what the future holds.
https://t.co/imkpT3iVNe
@rickoco#opensourceHW#opensource @DateConference
Don’t miss OpenHW TV Episode 3, Thursday 3.17 at 11am EST, Seeding the Next Generation of Innovators with Open-source RISC-V Processors. Here from OpenHW Group & ETH Zurich. Register today https://t.co/yH9WPXdMdh
@rickoco#opensourceHW#opensource@ETH_en@risc_v
Imperas unifies new open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse https://t.co/0cLcKbh8Fx
@ImperasSoftware @DanielNenni@risc_v#opensource#RISC-V #openhwgroup
OpenHW Group’s CEO @rickoco discusses the key drivers for growth of open-source processor development & latest milestones of the OpenHW Group https://t.co/Bjc7UV8J1s
@embedded_com#opensource@risc_v#risc_v @OpenSourceEmbed
Open Source Hardware & the Core-V family is the new reality. Check out our latest blog on open-source software projects https://t.co/NtdiDF6Man
#risc_v#opensource @ImperasSoftware @pulp_platform @OpenSourceEmbed
Learn about driving AI/ML innovation with CORE-V, Open-Source RISC-V Based Processors in today’s episode of OpenHW TV at 11am https://t.co/sQCqnUW31o
@risc_v#opensource@EclipseFdn @OpenSourceEmbed #risc_v
Learn how our working groups members are designing, verifying, and proving industry-quality RISC-V processor designs https://t.co/wMRzm2xx7H
@risc_v#opensource#openhwgroup@EclipseFdn#risc_v @OpenSourceEmbed
Catch up on the latest blog from Imperas - OpenHW Industrial-Grade Verification for Open-Source CORE-V IP Cores https://t.co/gH9Nhpwyhs
#risc_v#opensource#verification#corev
@ImperasSoftware
Join us today for a fireside chat on OpenHW TV with @embedded_com editor @ndahad and @rickoco Submit questions for the live Q&A at 11am EST. Register today https://t.co/gBUI0PE9KU