Top Tweets for #FPGAFriday
No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday
It's about time I updated my recommended #FPGA links. Send me a suggestion this #FPGAFriday. 😊 https://t.co/pQih9UCahl
Ok, that was #FPGAFriday after a two-week break to restructure and rework the subsystem.
I'm going my own way, just like CoreWally does. Though for me, CoreWally was a bit too complicated.
I'm moving everything out of the CPU core… next step: branch prediction and RAS!
@samsoniuk @ico_TC @fontamsoc @splinedrive @DutraCGI It will be a improved version of this https://t.co/2Ix1AUvMC0
Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @YosysHQ @machdyne @RadionaOrg https://t.co/S8uF1wG1rB
New Video Drop
👇⛏
Mining Hardware Update - What Am I Doing With My Osprey FPGA's Currently #FpgaFriday
https://t.co/8MFyEJfna2
A small rework discovered during #FPGAFriday using the ILA in Vivado :)
#RISCV #LINUX #XV6 #KIANV — The ultimate nano SoC to boot your OS!
https://t.co/jJqV4GER1u
So now I'm heading to the gym before I post too much crap on #fpgafriday. But maybe I'll work on the bootloader a little bit later. I want to replace the SD card stuff.
#FPGAFriday Atari 2600 on iCEBreaker.
Preparing for @tinytapeout on sky130.
RiverRaid is a very vivid memory from my early teens.
It's the little differences... that drive you mad when supporting multiple #FPGA dev boards. 😢
Supporting #SPI flash on @DigilentInc Arty S7 requires the STARTUPE2 primitive, while the A7 lets you access it via pin L16. #FPGAFriday
It's #FPGAFriday! Here's another peek at my current #FPGA project. This video shows Isle textmode, which supports coloured text (and backgrounds) and automatic scrolling. This capture is from Verilator/SDL, but it also runs on ECP5 and Xilinx 7 series FPGAs.
Sneak peek at the latest build of my new project for #FPGAFriday. I am currently testing it with my sponsors and will release it to everyone later this year. #FPGA #RISCV
Implementing micro SD card block for ❄️#icestudio and #verilog. Things appears start to work!! #FPGAWars #FPGA #FPGAfriday. Using opensource tools for debugging hardware in realtime, the amazing pulseview @sigrokproject
An FPGA? Yes!!!! driving an ADC⚡️?, Yes!!! this is REAL TIME acquisition using the GPU for REAL TIME FFT calculation, Hann windows, Hamming... and Yes!!!! ALL FROM THE BROWSER🤯. Prototyping new features for #icestudio . #FPGAwars #FPGA #FPGAfriday @Alhambra_bits @EladioDM
Wanted to post last #FPGAFriday, but I just got it working. Previously I had two types of GPU reg apertures: CPU settable via AXI and GPU settable via front end cmd buf packet. Happy to announce now the front end can write all regs, meaning cmd bufs can now submit other cmd bufs
My town has no water this weekend due to a burst pipe. I could use some #FPGAFriday inspiration right now. Show me your #FPGA projects, however big or small.
To get the ball rolling, here's a little video of a design I've been simulating.☀️
Again 😄 #FPGAFriday
💪After One Punch Man, One Pin Video has arrived⚡️😂.
B&W PAL video signal 📺, generated from a single pin of the FPGA (inout - tristate)🤯. Projects with few resources, retro👾...
Follow the thread at https://t.co/9Tu3OqXPUe #FPGAWars #icestudio #FPGAfriday #fpga #FPGAgaming
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