Juanma Rico

Impulsivo, imaginativo y creativo. Racional y reflexivo cuando consigo calmarme. Agresivo defendiendo mis ideas. Melancólico en soledad, payaso en compañía.

[Miguel A. Rodríguez-Jódar / mcleod_ideafix @zxprojects]

Generando la carta de ajuste de TVE, de manera procedural en una FPGA usando Verilog, sin tenerla guardada como un bitmap (excepto quizás para el logotipo de TVE). De momento, generadas las barras de rejilla, un cacho del círculo, el fondo con la rejilla y el rectángulo naranja

[Juanma Rico @juanmard]

@adumont ¡Buenas Alexandre!
Feliz año. Gracias por acordarte. 😉

Yo también las tengo abandonadas. El último SAV acabó en el «icestudio», pero lo han «manoseado» tanto que no merecía la pena seguir.

Temas de trabajo también me han apartado un poco. A ver si lo retomo yo también. 😊😊😊

[Juanma Rico @juanmard]

Aprendiendo a programar la @TinyFPGA en 'nMigen'.
Reescribiendo el código del 'game-pong'.
Ya rebota la pelota. 🤣🤣

https://t.co/rY4W7CXQf8

[Sylvain Lefebvre @sylefeb]

How much Quake can fit in a USB port? Quite a bit it turns out! A minuscule #Fomu #fpga board hosts my hardware/software re-implementation of the Quake render loop in the confines of a USB port (5K LUTs, 8 DSPs, all BRAMs, 128 kB of internal SPRAM). 1/n

[Antmicro @antmicro]

Renodepedia is a comprehensive database of boards, SoCs and vendors that makes navigating the hardware landscape simpler than ever before. Find out what it has to offer, including live demos, execution traces & metrics, logs, and more: https://t.co/USvclKraFj. @ZephyrIoT @risc_v

[Juanma Rico @juanmard]

https://t.co/aGFahE5KRP

[Antmicro @antmicro]

Our #opensource #SoC design developed as part of the @VEDLIoT project has been extended with a vendor neutral interface for connecting #AI/ #ML accelerators in #FPGA/ #ASIC designs. Read more in our latest blog post: https://t.co/ogEjPcxdB6 @VEDLIoT @CHIPSAlliance @renodeio #IoT

[Tim 'mithro' Ansell @mithro]

Super excited about the work @proppy is doing to put ASIC + FPGA tools into Jupyter notebooks!

You can then use them for free on @Google's Colab without having to install tools locally.

See the recent interview with @matthewvenn for more info - https://t.co/QairSB61RP

[Rodrigo Alejandro Melo @rodrigomelo9ok]

#FPGArgentina Nuevo lote de EDU-CIAA-FPGA disponible! (#FPGA #Lattice ICE40HX4K) https://t.co/zqeuRzjnZi

[Matthew Venn @matthewvenn]

March open source silicon news update!

* MPW5 & 6,
* 3d printed and laser cut standard cells,
* ASIC resources and lots more!

https://t.co/uG64SvzFw6

[f4pga @f4pga]

Data visualization generated by #CI is an important part of the #FPGA design process. If you’re familiar with #UX and #Python and want to help us improve the presentation layer of FPGA-tool-perf, sign up today for #GSoC:
https://t.co/V63j0a30pg @GoogleOSS @CHIPSAlliance @antmicro

[Juanma Rico @juanmard]

@matthewvenn A piece of mine are there! 😁

[Matthew Venn @matthewvenn]

Still can't quite believe I have a clock on my desk that is powered by a chip I designed!

[f4pga @f4pga]

Join #GSoC and help us expand the @F4PGA architecture definitions by adding support for DSP48E, improving coverage for real world designs in the F4PGA toolchain: https://t.co/0QxJMMMcW3 @GoogleOSS @CHIPSAlliance

[f4pga @f4pga]

An important part of the push towards open #FPGA is analyzing what we know about popular platforms such as the classic #Spartan6. If you like organizing information, sign up for #GSoC & help us document the Spartan6 bitstream: https://t.co/pcCTyARLcB @GoogleOSS @CHIPSAlliance

[Sylvain Lefebvre @sylefeb]

Two @risc_v cores, two memory interfaces, executing in parallel from shared spram and spiflash, ~2K LUTs. Coming soon in #Silice!
(red LED on core0, green LEDs on core 1)

[CHIPSAlliance @CHIPSAlliance]

Today CHIPS Alliance established the FOSS Flow For FPGA (F4PGA) Workgroup to drive open source tooling, IP and research efforts for FPGAs. Read more about our efforts to accelerate open FPGA innovation: https://t.co/Sf2y4VnC80

[Sylvain Lefebvre @sylefeb]

I've put the slides of my #doomchip talk online: https://t.co/0KEAAI3m2T (link to talk recording on first slide).

If you are wondering what a GPU for #Doom 1993 could have looked like, or are simply interested in Computer Graphics 'from scratch' (on #fpga), check it out!

[Enjoy Digital @enjoy_digital]

Hello NEORV32 CPU! 🥳 Only took a couple of hours to integrate it (thanks its excellent documentation). Working with litex_sim/Verilator (through GHDL-Yosys-Plugin) and on hardware (here on @DigilentInc Nexys Video). cc @unaimarcor @mithro

Test repo: https://t.co/e2kFM9wnSW

[ARCHIVED - Curiosity Rover @MarsCuriosity]

The Martian surface can be rocky, sharp, and unforgiving – so after nearly 10 years, my wheels have taken a beating. The good news is that this is not impacting my mission.

[Hans Baier @[email protected] @hansfbaier]

PicoSOC works on Kintex XC7K325T with full open source toolchain Yosys+nextpnr-xilinx