bibibibiii

@liwenchi2

Joined December 2018

30 Following

4 Followers

39 Posts

bibibibiii @liwenchi2

about 9 hours ago

@Ercanercoyeni 天才！

bibibibiii @liwenchi2

about 2 months ago

@WwQQ129146 铜冠铜箔，中钨高新

227

liwenchi2 retweeted

投研荟

@freearkshaw

about 2 months ago

摩根士丹利-亚太大中华区半导体：台积电前瞻与CoWoS更新——CPU、GPU、ASIC、光学、中国AI算力-TSMC preview and CoWoS update–CPU,GPU,ASIC,Optical,China AI Compute-20260706【58页】_sx68 报告核心投资结论第一主线：台��电，独家掌控 2nm/3nm+CoWoS 先进封装，涨价 + 扩产双驱动，AI 营收持续高增；第二主线：先进封装配��：CoWoS/SoIC 产能扩张带动 ASMPT、测试耗材（鸿准、MPI、WinWay）；第三主线：AI 芯片全链：英伟达产业链 + 云厂商自研 ASIC、国产 AI GPU；第四主线：存储原厂：HBM/NOR/DDR 持续紧缺，周期上行；中长期看点：Agentic 智能体 CPU、CPO 光电共封装、SiC 碳化硅功率器件。 https://t.co/6IgaMGOHCU

14K

liwenchi2 retweeted

投研荟

@freearkshaw

about 2 months ago

当下时点的液冷观点20260706 会议纪要 1.液冷产业正迎来重大产业变化。今年4月以来，液冷行业出现两个标志性事件：①英伟达Rubin平台将采用100%全液冷、45°C温水散热方案；②谷歌TPU V7和V8均已采用100%全液冷设计。这些变化标志着液冷正式��为AI算力的标配，产业进入放量元年。 2.市场对液冷存在三大误解：①认为液冷是配角——实际上液冷是核心主角，NV卡多次延后正是因为液冷散热卡脖子；②未认识到液冷是通胀环节和终局环节——未来无法回到风冷时代，且放量斜率��快，明年即达千亿级市场；③认为液冷格局分散——虽总体格局分散，但在CSP领域竞争格局良好，台资、日资、美资份额正被国内优质企业逐步替代。 3.投资节奏与核心标的：团队今年4月率先提示泵环节（CDU心脏）的投资机会，精准判断泵将在Q2提前采购，飞龙股份、大元泵业已取得不错涨幅。当前重点关注液冷五朵金花：英维克、申菱环境、飞龙股份、大元泵业、银轮股份。其中英维克处于业绩兑现前的“盛红”阶段，Q3业绩兑现的可能性较大，一旦兑现空间可观。 4.核心零部件竞争格局优：CDU中的泵和板式换热器环节技术壁垒高、竞争格局好（泵仅少数几家、板换约4家），毛利率和净利率可观，值得持续关注。 5.三季度关注度将持续提升：Rubin和TPU出货将带来大量市场讨论，同时是验证国内企业海外订单突破的关键期，若有业绩兑现，有望引发大行情。

13K

liwenchi2 retweeted

Macro_Lin

@LinQingV

about 2 months ago

I've been discussing Huawei's τ scaling (temporal scaling) with people recently, and noticed the conversation tends to stay at the surface level without reaching its substance — likely because many participants don't come from an EE background and aren't familiar with the classical meaning of τ in circuit theory. The very first time constant you learn in a circuits course is τ = RC: the resistance of a wire multiplied by its capacitance gives the order of magnitude of the time a signal needs to traverse that wire. The longer the wire, the greater the resistance and capacitance, and the slower the signal. Within this framework, the past sixty years of geometric scaling are reinterpreted as one particular implementation of temporal scaling. Transistors were shrunk to shorten switching delay; circuits were packed more tightly to shorten metal interconnects and reduce signal propagation delay. Geometric scaling was only ever the means — compressing delay was always the end. Huawei's thesis is that once geometric scaling stalls, you find other ways to keep compressing delay. As it happens, He Tingbo's τ scaling paper released its v2 a couple of days ago, expanding from 16 to 23 pages. I compared the two versions: the data and conclusions are unchanged. The additions are essentially responses to several points of criticism the industry raised about v1. Three are worth discussing. The most important addition is the test evidence now backing the previously bare claim of "41% energy efficiency improvement." In v1, that number had no baseline and no test conditions — the most obvious target for scrutiny. V2 supplies a full comparison table. The baseline is the 2025 Kirin 9030 Pro. Both chips use the same mature process node; the key difference is that the baseline uses a conventional planar design, while Kirin 2026 folds critical paths across two vertically bonded wafers. Folding shortens interconnects and reduces interconnect delay. The timing margin freed up on the critical path translates directly into a higher maximum clock frequency: 3.1 GHz at 1.1 V supply, 13% above the baseline. The "41% energy efficiency improvement" comes from a separate operating point specifically configured for an iso-performance comparison: voltage scaled down to 0.9 V, frequency scaled down to 2.5 GHz, with measured power at 25°C coming in at 0.59× the baseline. A back-of-the-envelope estimate checks out: dynamic power scales roughly with the square of supply voltage, so an 18% voltage reduction contributes about one-third of the power drop from the square term alone. Factor in the 9% frequency reduction and the interconnect capacitance eliminated by folding, and you land right around 0.59×. So the precise meaning of "41% energy efficiency improvement" is power reduction at iso-performance. In essence, the timing margin gained from folding is traded for lower power consumption; the efficiency gain comes from logic folding. As a side note, v2 also reports that power density after dual-layer stacking is actually 5.6% lower than the baseline. The second addition addresses the question peers are most likely to ask: 3D stacking has been around for years — AMD's 3D V-Cache and Intel's Foveros are both in volume production — so what's new about LogicFolding? To understand the paper's answer, you first need to know how two layers of silicon communicate. They rely on inter-layer bond pads, which function like elevators connecting the upper and lower floors. In prior production 3D stacking, bond pad pitch ranges from 9 μm to tens of micrometers, yielding roughly ten thousand connections per square millimeter — enough to attach a bus to an entire cache block. So the established design approach has been to move complete functional blocks wholesale onto the upper tier. AMD, for example, stacks an entire cache die on top of a processor die; the two tiers are designed independently and connected through an interface. But inside a chip, a single square millimeter contains hundreds of millions of transistors. If you want adjacent logic gates to sit on different tiers — one on top, one on the bottom — that connection density falls far short. Kirin 2026 brings bond pad pitch down to 1.5 μm, yielding 440,000 connections per square millimeter. That approaches the density of the top-level metal wiring inside a chip. Routing a signal across tiers costs roughly the same as routing it across metal layers within a single die. At this point, the two silicon layers merge into a single entity in the circuit sense. EDA tools can decide at the individual logic-gate level which gate goes on which tier, handing the problem to algorithms for global optimization — a completely different degree of design freedom from what came before. The paper also explains why they didn't take the more aggressive route of fabricating a second device layer directly on top of the first. That approach offers the finest inter-layer connectivity, but manufacturing the second layer requires high temperatures that damage the already-completed first layer. It isn't production-viable today. The third addition is thermal management. Vertical stacking significantly increases thermal density per unit area, and the lower die's heat dissipation path is blocked by the upper die. This is the first objection anyone raises about 3D stacking, and v1 did not address it in depth. V2 openly acknowledges that thermal management remains a key challenge for the LogicFolding architecture. The countermeasure is thermally-aware partitioning and floorplanning: during the design phase, high-power circuits are excluded from folding candidates, and the floorplan avoids placing high-power blocks in vertical adjacency to prevent hotspot superposition. Whether this strategy is a set of manually imposed engineering constraints or has already been codified into an automated flow within their internal EDA tools, the paper does not say. It only identifies a multi-physics tool chain as the single most important investment for the next decade. Combined with the measured data showing power density 5.6% below the baseline at the iso-performance operating point, the thermal concern has at least received a direct response. That said, this approach is fundamentally avoidance-based. As stacking grows to three or four tiers, the design space eligible for folding will be progressively squeezed by thermal constraints — a boundary the paper does not explore. Additionally, v2 includes a cross-sectional micrograph of the bond interface between the two wafers and explicitly states that wafer-on-wafer hybrid bonding is used. This spec is worth benchmarking against the industry: 1.5 μm pitch wafer-to-wafer hybrid bonding on a production logic chip has no precedent. TSMC's SoIC is currently in production at 6 μm pitch; Intel's Foveros Direct is at 9 μm. Impressive, to say the least. After comparing the two versions, I'm left with two questions. One is about equipment: who supplied the bonding tools capable of this spec? The paper says only that it is the result of years of process development across a multi-vendor ecosystem. The other is about EDA: designing two wafers as a single chip is beyond what any commercially available EDA tool can do today. The paper acknowledges this, stating only that methodological details will be "published within months." Yet the frequency table shows that the 2027-generation Kirin at 3.39 GHz is already tagged as having physical silicon, meaning this toolchain was up and running inside Huawei long ago — and has been validated on at least two product generations. My personal guess is that this EDA capability was built in-house by Huawei. If anyone has insight on this, I'd welcome the discussion.

LinQingV's tweet photo. I've been discussing Huawei's τ scaling (temporal scaling) with people recently, and noticed the conversation tends to stay at the surface level without reaching its substance — likely because many participants don't come from an EE background and aren't familiar with the classical meaning of τ in circuit theory. The very first time constant you learn in a circuits course is τ = RC: the resistance of a wire multiplied by its capacitance gives the order of magnitude of the time a signal needs to traverse that wire. The longer the wire, the greater the resistance and capacitance, and the slower the signal. Within this framework, the past sixty years of geometric scaling are reinterpreted as one particular implementation of temporal scaling. Transistors were shrunk to shorten switching delay; circuits were packed more tightly to shorten metal interconnects and reduce signal propagation delay. Geometric scaling was only ever the means — compressing delay was always the end. Huawei's thesis is that once geometric scaling stalls, you find other ways to keep compressing delay.

As it happens, He Tingbo's τ scaling paper released its v2 a couple of days ago, expanding from 16 to 23 pages. I compared the two versions: the data and conclusions are unchanged. The additions are essentially responses to several points of criticism the industry raised about v1. Three are worth discussing.

The most important addition is the test evidence now backing the previously bare claim of "41% energy efficiency improvement." In v1, that number had no baseline and no test conditions — the most obvious target for scrutiny. V2 supplies a full comparison table. The baseline is the 2025 Kirin 9030 Pro. Both chips use the same mature process node; the key difference is that the baseline uses a conventional planar design, while Kirin 2026 folds critical paths across two vertically bonded wafers. Folding shortens interconnects and reduces interconnect delay. The timing margin freed up on the critical path translates directly into a higher maximum clock frequency: 3.1 GHz at 1.1 V supply, 13% above the baseline. The "41% energy efficiency improvement" comes from a separate operating point specifically configured for an iso-performance comparison: voltage scaled down to 0.9 V, frequency scaled down to 2.5 GHz, with measured power at 25°C coming in at 0.59× the baseline. A back-of-the-envelope estimate checks out: dynamic power scales roughly with the square of supply voltage, so an 18% voltage reduction contributes about one-third of the power drop from the square term alone. Factor in the 9% frequency reduction and the interconnect capacitance eliminated by folding, and you land right around 0.59×. So the precise meaning of "41% energy efficiency improvement" is power reduction at iso-performance. In essence, the timing margin gained from folding is traded for lower power consumption; the efficiency gain comes from logic folding. As a side note, v2 also reports that power density after dual-layer stacking is actually 5.6% lower than the baseline.

The second addition addresses the question peers are most likely to ask: 3D stacking has been around for years — AMD's 3D V-Cache and Intel's Foveros are both in volume production — so what's new about LogicFolding? To understand the paper's answer, you first need to know how two layers of silicon communicate. They rely on inter-layer bond pads, which function like elevators connecting the upper and lower floors. In prior production 3D stacking, bond pad pitch ranges from 9 μm to tens of micrometers, yielding roughly ten thousand connections per square millimeter — enough to attach a bus to an entire cache block. So the established design approach has been to move complete functional blocks wholesale onto the upper tier. AMD, for example, stacks an entire cache die on top of a processor die; the two tiers are designed independently and connected through an interface. But inside a chip, a single square millimeter contains hundreds of millions of transistors. If you want adjacent logic gates to sit on different tiers — one on top, one on the bottom — that connection density falls far short. Kirin 2026 brings bond pad pitch down to 1.5 μm, yielding 440,000 connections per square millimeter. That approaches the density of the top-level metal wiring inside a chip. Routing a signal across tiers costs roughly the same as routing it across metal layers within a single die. At this point, the two silicon layers merge into a single entity in the circuit sense. EDA tools can decide at the individual logic-gate level which gate goes on which tier, handing the problem to algorithms for global optimization — a completely different degree of design freedom from what came before. The paper also explains why they didn't take the more aggressive route of fabricating a second device layer directly on top of the first. That approach offers the finest inter-layer connectivity, but manufacturing the second layer requires high temperatures that damage the already-completed first layer. It isn't production-viable today.

The third addition is thermal management. Vertical stacking significantly increases thermal density per unit area, and the lower die's heat dissipation path is blocked by the upper die. This is the first objection anyone raises about 3D stacking, and v1 did not address it in depth. V2 openly acknowledges that thermal management remains a key challenge for the LogicFolding architecture. The countermeasure is thermally-aware partitioning and floorplanning: during the design phase, high-power circuits are excluded from folding candidates, and the floorplan avoids placing high-power blocks in vertical adjacency to prevent hotspot superposition. Whether this strategy is a set of manually imposed engineering constraints or has already been codified into an automated flow within their internal EDA tools, the paper does not say. It only identifies a multi-physics tool chain as the single most important investment for the next decade. Combined with the measured data showing power density 5.6% below the baseline at the iso-performance operating point, the thermal concern has at least received a direct response. That said, this approach is fundamentally avoidance-based. As stacking grows to three or four tiers, the design space eligible for folding will be progressively squeezed by thermal constraints — a boundary the paper does not explore.

Additionally, v2 includes a cross-sectional micrograph of the bond interface between the two wafers and explicitly states that wafer-on-wafer hybrid bonding is used. This spec is worth benchmarking against the industry: 1.5 μm pitch wafer-to-wafer hybrid bonding on a production logic chip has no precedent. TSMC's SoIC is currently in production at 6 μm pitch; Intel's Foveros Direct is at 9 μm. Impressive, to say the least.

After comparing the two versions, I'm left with two questions. One is about equipment: who supplied the bonding tools capable of this spec? The paper says only that it is the result of years of process development across a multi-vendor ecosystem. The other is about EDA: designing two wafers as a single chip is beyond what any commercially available EDA tool can do today. The paper acknowledges this, stating only that methodological details will be "published within months." Yet the frequency table shows that the 2027-generation Kirin at 3.39 GHz is already tagged as having physical silicon, meaning this toolchain was up and running inside Huawei long ago — and has been validated on at least two product generations. My personal guess is that this EDA capability was built in-house by Huawei. If anyone has insight on this, I'd welcome the discussion.

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bibibibiii @liwenchi2

about 2 months ago

@STOCK6688 华丰科技上周五上车的

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liwenchi2 retweeted

animajoe0917

@JoeAnima

2 months ago

不吹牛皮，这是东半球写的最详细的

807

165

817

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liwenchi2 retweeted

@RJDAIGOGO

2 months ago

可能是我最近看过的最好的一个讲高带宽内存HBM的视频，从基本原理讲到工程工艺，顺便比较了一下内存三巨哪家强。深入浅出，推荐观看。

661

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liwenchi2 retweeted

Lucy L.

@LucyBuilding

3 months ago

我想研究【公司名】所在的【行业/细分业务】。请你不要直接评价这家公司好不好，而是假设我是一个资金充足、执行力很强的新进入者，准备从 0 开始做同样的生意，并在【3-10 年】内挑战【公司名】。请你站在三个视角分析：创业者/竞争对手视角：如果我要从 0 做起来，我会被卡在哪里？产业研究员视角：这个行业真正的关键资源和利润来源是什么？长期投资者视角：这家公司是否具备可持续护城河，是否值得长期跟踪或持有？在回答前，请先做 3 件事： A. 明确业务边界请��说明【公司名】到底靠哪些业务赚钱，不要把公司简单等同于一个行业。例如：它是产品公司、平台��司、渠道公司、基础设施公司、资源型公司，还是多种模式叠加？ B. 区分事实、推断和假设请在分析中明确标注：已确认事实基于事实的合理推断需要进一步验证的假设 C. 如果信息不足，请不要编造请直接说明哪些信息需要查年报、财报电话会、投资者日、行业报告、监管文件或客户/供应链数据验证。请按以下框架拆解：一、行业从 0 做起来的完整流程假设我是新进入者，从 0 开始做这个行业，请拆解完整流程：我要先解决什么问题？需要做出什么产品或服务？需要哪些核心技术？需要哪些供应链资源？需要哪些基础设施？需要哪些人才和组织能力？需要哪些销售渠道和客户关系？需要多少资金，资金主要花在哪里？需要哪些监管、牌照、认证或政策支持？从启动到商业化，大概需要多久？请不要只列清单，要说明每一步为什么重要。二、��入这个行业最难的 5-7 个环节请找出这个行业最难突破的 5-7 个关键环节。每个环节请说明：难在哪里需要多少钱需要多长时间需要哪些稀缺资源新进入者最容易死在哪里有钱能不能解决如果不能完全靠钱解决，真正缺的是什么三、目标公司在关键环节里的位置请分析【公司名】在上述关键环节里分别占据什么优势。请区分以下类型：技术优势产品优势成本优势规模优势客户关系渠道优势数据优势生态优势品牌信任监管/牌照优势资本开支和融资能力供应链卡位基础设施卡位时间窗口和先发优势请进一步判断：这些优势是“强护城河”“阶段性优势”，还是“容易被竞争对手追平的优势”？四、竞争对手攻击模拟假设我是竞争对手，分别给我三档预算：低预算：【金额】中预算：【金额】高预算：【金额】请分别告诉我：第一年度我应该做什么？三年内我能追上【公司名】哪些部分？哪些部分即使有钱也很难追上？我最现实的切入点在哪里？我应该正面进攻，还是绕开它？如果绕开它，最好的细分市场是什么？如果正面进攻，最大风险是什么？我最终有多大概率撼动它的核心地位？五、护城河压力测试请不要泛泛而谈“品牌、技术、规模”。请判断【公司名】真正的护城河是什么，并回答：这个护城河来自哪里？它是技术壁垒、客户锁定、成本优势、网络效应、监管优势、供应链优势，还是资本密集带来的进入门槛？这个护城河能不能转化为利润？它能不能提高毛利率、经营利润率、自由现金流或 ROIC？它能持续多久？它会不会被新技术、新商业模式或政策变化绕开？什么情况下这个护城河会失效？如果我是竞争对手，攻击这个护城河最有效的方法是什么？六、财务和商业模式验证请从投资角度进一步分析：这家公司的收入增长来自哪��？增长是靠行业扩张、价格提升、份额提升，还是并购/资本开支驱动？毛利率和经营利润率是否能稳定或提升？自由现金流质量如何？资本开支是��护性投入，还是扩张性投入？资产负债表是否能支撑长期扩张？公司增长是否依赖少数大客户？如果公司现在大幅投资，未来能否形成更高利润和现金流？这个商业模式更像轻资产软件、重资产基础设施、周期品，还是平台型生意？七、长期持有判断请不要直接给“买/卖”建议，而是判断它是否具备长期跟踪或长期持有的条件。请输出：长期看好的核心逻辑短期市场担心什么哪些担心是合理的哪些担心可能是市场过度反应未来 3 年最重要的 5 个验证指标一旦出现哪些信号，说明投资逻辑变了什么情况下可以安心持有什么情况下必须重新评估这家公司适合什么类型的投资者，不适合什么类型的投资者八、最后请给出一个结论请用以下格式总结：一句话判断这家公司真正的生意是什么。一句话判断它最核心的护城河是什么。一句话判断竞争对手最难复制的地方是什么。一句话判断市场目前最担心什么。一句话判断未来最值得验证的指标是什么。最后给出一个结论：这家公司是“短期被高估的叙事”，还是“正在把投入转化为长期壁垒的公司”？请说明理由。

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bibibibiii @liwenchi2

3 months ago

@mindmoon_108 请问如何看待半导体测试技术在这一轮行情中的地位。

liwenchi2 retweeted

K三凯

@kaikaibtc

3 months ago

我把Serenity和Crux这两个美股狂魔，蒸馏成了一个自动投研的Agent 上周我扒了 Serenity（@aleabitoreddit）的 1073 条推文，5 个月 32 倍。这次我又扒了第二个人——Crux Capital（@crux_capital_），五个月 647 条原帖，126 个价值票。 Serenity窄而深：找一个制胜点，押死。 Crux 宽而有纪律：画一张六层栈，每层按执行力排仓位。看完我有点难受，不是因为收益图太夸张。是我发现，这两个人��的根本不是传统意义上的“选股”。他们是在搭一条投研流水线， AI 负责搬砖，人负责最后拍板。 1⃣ 他们的方法论：先拆机器，再找堵点他们看一个赛道，不先问“谁会涨”。先问的是：这台机器到底长什么样？ BOM 里最难替代的零件是什么？如果其中一家明天停产，下游要等多久？这个问题一问出来，视角就完全变了。大家还在盯 GPU、HBM、电力这些第一层热点时，他们已经往下抠第二层、第三层：激光器、InP 衬底、外延、测试、连接、冷却、配电…… Serenity 最狠的地方，是死盯单点故障。 Crux 更像工程师，先画一整张栈，再给每层贴标签：谁是龙头，谁是瓶颈，谁只是会讲故事，谁又是那种没人聊、但每台机器都得用的“无聊必需品”。 2⃣AI 在他们手里，不是军师，是苦力普通人用 AI 做投资，喜欢问： “这票能买吗？” “帮我总结一下财报。” “这个赛道有没有机会？” 这种问法，说到底还是在等答案。他们不是这么用的，他们让 AI 去干最脏最累的活：拆机器，顺着零件找供应商，再找供应商的供应商，横着读多家公司财报和电话会，把“产能打满”“认证快结束”“明年放量”这些零碎信号拼成一张图。说白了，AI 没替他们赚钱，AI 只是把研究量的上限硬抬上去了。 3⃣所以我把这套东西蒸馏成了一个 skill https://t.co/V6OUO1IuJZ 它不干一件很俗的事：上来就给你甩股票代码。它先跑五步： L1 先确认终端，到底研究的是哪台机器、哪套系统 L2 再画供应链栈，搞清楚谁在第几层 L3 找真正的卡点，卡的是产能、认证、热、电、良率，还是材料 L4 用财报、产业新闻、研报交叉验证 L5 先给方向，再给名字，最后才谈仓位我蒸馏的不是他们买了什么，我蒸馏的是他们怎么提问，怎么排除，怎么把热闹拆成一个个能验证的环节。 4⃣举个例子，人形机器人接下来该买什么大部分人第一反应都是特斯拉、英伟达、总龙头。但这个 skill 不会先看这些。它会先问：如果 Optimus 真开始放量，最先紧张的是哪一层？如果谐波减速器已经被市场盯得很紧，那下一步就该继续往旁边看：每个关节都离不开的力传感器，有没有被认真定价？重点不是马上得出“买谁”。重点是先知道：你该查哪一层。顺着这套方法继续往后推，我现在最想深挖的，反而不是更拥挤的 GPU 叙事。而是AI factory 的供电 + 液冷 + 物理交付层。原因很简单。芯片再猛，电接不进去也白搭。柜子再多，热散不掉也白搭。模型再聪明，机房交不出来，还是得排队。这条线不性感，不热闹，也不太适合吹牛。但真缺了它，项目就只能往后拖。最后看完 Serenity 和 Crux，我最大的感受其实挺扎心的： AI 没有让投研变轻松。它只是先把偷懒的人淘汰了。以后谁再跟我说 “AI 会让投资越来越简单” 我大概只会回一句：简单个屁，马太效应罢了，你有的他给你更多，你没有的，他把你已有的都给抢走。