Reconfigure.io

The next stage in computing power

[Alex Bradbury @asbradbury]

Really excited to be able to reveal @lowRISC's closer collaboration with Google and ETH Zurich. https://t.co/UMSGSh7ayI New board members and an exciting development roadmap made possible by the support and funding from Google. Also, we're hiring! https://t.co/Oz1cX6rESM

[Carlos Eduardo (@[email protected]) @carlosedp]

Just merged @golang x/sys module with latest #RiscV assembly code and now the GC works! Successfully built go-Jsonnet and a webserver with Echo(https://t.co/CfvLsKmj82). @golangnews @jessfraz @SiFive @palmer_dabbelt @justincormack @risc_v @marco_peereboom @labstack #golang

[Jamie Bartlett 🇬🇧 @JamieJBartlett]

I can’t believe what I’m seeing! While running a facial recognition pilot, one man (understandably imho) covered himself up. The police forced him to show his face (& then fined him for disorderly conduct). This is dangerous & terrifying.

[Claire Xen 🏳️‍⚧️🧙🏻‍♀️ 💖💛💙 BLM 🏴🚩 @oe1cxw]

Our FCCM short paper is now on arXiv:

Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs.

David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanović.

https://t.co/MILrfUyIFv

[Nanotech Commercialisation Experts @BREC_Ventures]

Not quite the silver bullet, certainly not yet, in compute. Performance v cost (key driver still post-Moore’s Law) is fast being advanced with hardware such as FPGAS & numerous software/architecture developments. #Nanotechnology is speaking louder in compute but has a way to go.

[SymbiFlow @symbiflow]

You might not be aware, but SymbiFlow can synthesize @linuxfoundation #Linux and @ZephyrIoT capable @RISC_V SoCs today. Participate in @GSoC - applications close in 5 days so be fast! - and help us open up #FPGA tooling to accelerate innovation in FPGAs: https://t.co/nKOAexXx7r

[Jon Masters 🏴‍☠️ @jonmasters]

I feel like if @intel and @alteracorp want to really shake things up they should apply their usual love of Open Source to FPGA bitstreams and support open synthesis and place+route for their FPGAs. Sure, patents and IP and stuff, but they've a big arsenal to defend against trolls

[Nanotech Commercialisation Experts @BREC_Ventures]

One-size-fits-all #investment models don’t suit #Nanotechnology due to horizontal & enhancing/enabling characteristics. Research, government initiatives, collaborations, JV’s, corporate venture, #tech licensing, equity/debt and M&A all need to be considered within a nuanced mix

[PULP Platform @pulp_platform]

Boot SMP Linux on @OpenPiton+ Ariane🚀! The Princeton Parallel Group and IIS ETH are bringing you the first Linux-booting, open-source RISC-V system that scales from single to manycore. Download 1, 2 and 4-core FPGA bit files here: https://t.co/DikNWyDy9R
https://t.co/jpf9P6UXoT

[FOSSi Foundation @FossiFoundation]

Find it hard to keep track of all the great Open Source Silicon events? Don't worry. We have collected them all at https://t.co/Q8xcPZ8F49

First up is @LatchUpConf followed by Week of Open Source Hardware (WOSH) together with @risc_v @eurolab4hpc and @pulp_platform

[Jim Carroll @ConvergeDigest]

Microsoft is open sourcing Project Zipline to spur faster implementation in silicon #OCPSummit19

[Jan Gray @jangray]

#FPGA Essential reading. Composing FPGAs and data center resources at scale with Direct Univeral Access. https://t.co/llN1luX8dc

[FOSSi Foundation @FossiFoundation]

Today is the best second Tuesday of the month as we once again bring you the @librecores newsletter with the latest news from the buzzing world of free and open source silicon featuring @risc_v @OpenPiton @SpinalHDL @pulp_platform @WesternDigiCTO and more https://t.co/VvoGLTRhdc

[Jan Gray @jangray]

#FPGA #RISCV

[Seraphim Space Accelerator @SeraphimSpaceVC]

They've done it. Congrats to @SeraphimCapital portfolio company @iceyefi for the success of their mission. Following ICEYE-X1, the world's first SAR satellite under 100kg in mass, ICEYE-X2's use cases will include flood extent monitoring, vessel detection and field segmentation.

[The New Stack @thenewstack]

.@awscloud has also created a new chip, a “AWS Inferentia,” a latency-sensitive high-throughput processor for #ml inferencing. Supports all major #ai frameworks, can be attached to #EC2 instances and also available with #SageMaker — @ajassy #AWSreInvent2018

[Seraphim Space Accelerator @SeraphimSpaceVC]

Mission 1 was a huge success. They have secured or have offers for £4m+, continue to engage with our corporate partners, have hired 15 new staff and have set up several new offices in the UK #SpaceTech #Mission2

[Reconfigure.io @ReconfigureIO]

Reconfigure v0.18.3 is released 🎉 We're getting closer to adopting our reworked compiler, read more here: https://t.co/5XgAzodyTv #FPGA #golang #startup #acceleration

[Mahdi Jelodari @MJcomp86]

"future systems have to use lower clock frequencies to keep power consumption down, and use larger number of cores to push performance up." sounds very familiar.. #FPGAs https://t.co/Hymc5cbjYz