Still pretty much WIP, hopefully in time to submitted for MPW7… (This is an open-source implementation of a dual-issue RV64 processor with a 5GHz transceiver using SKY130B CMOS technology, digital and top l-level hardened using SiliconCompiler with yosys and openroad)
SiliconCompiler 0.9.4 has ben released, lots of goodies! New @OpenROAD_EDA version, new surelog, cleaner summary reports, updated skywater130 flow.
$ pip install siliconcompiler
https://t.co/AMdiiLNOUg
ICYMI, Zero ASIC is profitable and growing fast! Join us to fix the proplem with run away chip design costs. Tell your friends. https://t.co/Mepx9V0oVj
We created an SC based https://t.co/Dzu5XIVLJa that emulates the Makefile behavior in @OpenROAD_EDA, giving us access to OpenRoad's awesome suite of tests and benchmarks.😎 https://t.co/YPQ5gAEfhu @mithro@tomspyrou@proppy@matthewvenn
Thanks to our DAC59 trip there are now 100+ designers familiar with the open source @siliconcompiler. At $0 per designer, we are going to be rich🤣Presentation + Paper: https://t.co/vEfsXBDzZw
https://t.co/sOuFcLLvoh
If you are going to DAC in SF next week, come see our cool new @siliconcompiler demos in booth #2330. This is the first time there is an "open source central" at DAC. Exciting times! https://t.co/Ce2EIv21vF
Happy Friday! A major update to SiliconCompiler is now live! [0.9.0]
$ pip install --upgrade siliconcompiler
https://t.co/AtH0gUw59S
So many improvements! [1/n]