@no1089@matthewvenn@UriShaked and to REALLY show off there's this "ttihp-oscillating-bones" ring oscillator project he created, using the skullFET.
https://t.co/9YUjk4a9kI
We already have some nice looking entries into our #demoscene competition!
There's still 33 days to go, but don't leave it too late! Start on your entry today:
https://t.co/9A2keuJ72t
#ASIC#opensource#TinyTapeout
Meet the awesome judges of our #ASIC demoscene competition: Jeri Ellsworth, Will Flux and Sprite_tm!
https://t.co/9A2keuJ72t
#opensource#ASIC#competition
Very happy to announce the winners of our demoscene competition! 🏆
We had some amazing entries - check out what can be done in just a few square microns of silicon!
https://t.co/zWHVdJG37b
Thanks again to our judges and participants!
#silicon#demoscene#ASIC
Finally, we’re ready to announce the demoscene competition winners!🎉
Join us live Wednesday the 11th at 19:00 CET to find out who won and to hear how our amazing judges chose the winners.
Click “Notify” on the stream to get an alert when we go live: https://t.co/d45PkbU81Q
A truly inspiring talk by @UriShaked@BsidesTLV on democratizing chip making with @tinytapeout.
It's a "WeWork for chips": Instead of paying for a "full office" (chip), independent devs can pay for just a few "rooms" (tiles) + enjoy additional services ( e.g. demo board)
Working on a Z80 replica for @mithro’s https://t.co/mrZyXPFbPk tapeout in a couple of days. 180nm proces and 5 mm^2 die area could be a perfect match for reviving retro chip manufacturing! FOSSi, open source silicon.
🚀 Bringing My Own Silicon to Life
For many years, hardware has been a hobby I've been passionate about. Over that time, I've brought several kewl projects to life- but this one is different.
Over the past few months, I've been slowly learning and working on something that still feels surreal: designing and taping out my own silicon chip through the @tinytapeout program.
My project: a SHA-256 processor- is part of the TTSKY25A Multi-Project Wafer shuttle (launching in 3 days!), built on the Sky130 PDK (SkyWater 130nm technology) and based on the open-source Caravel framework. I designed it from scratch in Verilog, iterated across multiple versions, and optimized it to fit within the ultra-tiny 4×2 tile footprint.
What started as curiosity about how cryptographic cores could be implemented at the transistor level turned into hours of:
🔹 Debugging synthesis and placement with OpenLane
🔹 Experimenting with ROM macros vs. algorithmic constant generation
🔹 Shrinking designs to squeeze performance into just a few thousand gates
🔹 Learning how PDN pitch, macro placement, and even tap cells can make or break a layout
Another kewl part? Early next year, I'll be holding an actual silicon die in my hands that runs code I wrote and logic I designed.
We often take for granted the chips powering our world- phones, servers, AI accelerators... Going through this process firsthand gave me a deeper appreciation for just how much ingenuity and effort goes into every square millimeter of silicon.
I like what Alan Kay once said: "People who are really serious about software should make their own hardware." Well, I think I'm starting to consider myself serious about software 😉
Excited to keep pushing forward with open-source tooling, community knowledge, and the chance to explore hardware design in such a hands-on way.
Huge thanks to @UriShaked , Matt Venn, Pat Deegan, and the @tinytapeout community for helping me out through this process!
💡 If you’re curious about Tiny Tapeout or ASIC design, I'd be happy to share more on my experience - this has been one of the most rewarding learning journeys I've taken.
Feel free to check out my project here: https://t.co/65y3bSYt88
#tinytapeout #sky130 #chipdesign #opensourcesilicon #tapeout
@PsychogenicTech@always_ff_rohan@tinytapeout@fishPointer I found a past chat with actual numbers:
running my TT07 mandelbrot set accelerator, which fits into 12 TT tiles, used 8673 LCs (164%).
I tried to use the DSPs, was barely able to fit the LCs (4944), but ran out of DSP units (needed 12, had 8)
https://t.co/juVXKSQfFJ
Our chip viewer just got an upgrade: now you can see microscope images, GDS, local interconnect and jump straight to project files. Spot something cool? Dive right into the design.
https://t.co/EZkIw6tDeb
Try out our new layer selections with the button at the top right.
FabricFox: Little FPGA board that's a drop-in replacement for the ASIC on @tinytapeout TT06+ demo boards. It'll be CRAM configured by the RP2 on the DB, so it's uber simple. @fishPointer : does this save me from the culling?