HEROv2's compiler makes software-managed memory hierarchies as easy to program as HW-managed caches. It can tile data structures & insert DMA transfers, achieving up to 90% of the performance of painstakingly hand-tuned code.
https://t.co/XVQFcoyNdr
https://t.co/mBwvWucga8
And that's not all - HEROv2's runtime stack seamlessly integrates accelerators into Linux running on the host to enable heterogeneous applications with transparent offloading of accelerated kernels.
https://t.co/mBwvWtUFiA
https://t.co/XVQFcoQoC1
Did you know that our recently released HEROv2's LLVM toolchain combines 64-bit host and 32-bit accelerator compilers, so that you can seamlessly share code and data in heterogeneous applications?
https://t.co/mBwvWtUFiA
https://t.co/XVQFcoQoC1
In conjunction with our HEROv2 release we published "HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing" https://t.co/mBwvWtUFiA.
Did you know that HEROv2 combines a 64-bit general-purpose host CPU with a 32-bit programmable many-core accelerator?
This is a pretty big deal. A major @pulp_platform release, a big step forward with multiple MYs of collettive work, pulled together by @accuminium 😎! Also thanks to @llvmorg we can offload smoothly from ARM64 to @risc_v RV32. Very proud of the team's accomplishment!
The new version of HERO just came out! We are giving you HEROv2, our FPGA-based full-stack open-source research platform for heterogeneous computing. Check it out on github: https://t.co/XVQFcoQoC1
Thank you @accuminium for all the info.
The Ibex RISC-V core is evolving remarkably! Interesting blog post by @lowRISC's @vogelpi -- thanks for your very valuable contributions to the open-source HW and RISC-V community!
All the photos from the #RISC-V workshop in Zurich are now online. 📸😃
https://t.co/ZcqJ1Ig0Wc
Thank you to Andreas and Frank for all the effort. @accuminium@risc_v@FossiFoundation
And in the parallel session we have Andreas from our team giving a tutorial on PULP's HERO, our Open Heterogeneous Research Platform. #WOSH
https://t.co/qsa1RKaY1x @accuminium
@pulp_platform My pleasure! Thanks to all organizers and attendees for making #RISCVWorkshopZurich a great experience! 👏 All photos will be online soon, follow @pulp_platform to not miss them -- and stay in Zurich for more great content at #WOSH!
1/2 A great talk by David Patterson introducing Embench TM for embedded IoT computers and discussing the characteristics of a good benchmark. What are these?
1. it has to be free
2. easy to port and run
3. must be a suite of real programs
4. must have a supporting organisation
Very pleased to be launching our new global non-profit focused on open source HW innovation. Our #CORE-V family of open source @risc_v cores are based on the great work form the @pulp_platform team. More details here https://t.co/gFU2FPumQB
This talk will present the HERO platform, its current OpenMP 4.5 support and the benefits OpenMP 5.0 may uncover. HERO is an open-source @pulp_platform featuring a cluster of @risc_v cores. Join us on June 5 @EPCCed Edinurgh. Details at: https://t.co/7Rt3VBncRC @eurolab4hpc
Delighted to confirm invited talk: "HERO Towards OpenMP 5.0" from @pulp_platform for this years UK OpenMP Users Conference - 4-5 June @EPCCed - Call for other submissions closes this Sunday, April 7. https://t.co/7Rt3VBncRC
Great series of articles about @risc_v on @eetimes. Having preached about FOSSi for a decade now, I know that RISC-V has a bright future. But I agree with @jonmasters that standardization (preferably CPU-agnostic) on all levels is super important. CPU!=SoC https://t.co/06kbtRIU1p