PDVL

PDVL is an aspect oriented and transaction level Programming, Design and Verification Language. Free & #OS HW\SW #SystemVerilog #Verilog #VHDL #UVM #SVA #PSL

[PDVL @PDVLcc]

@unaimarcor Is there any target date by when a proposal must be submitted ?

[PDVL @PDVLcc]

It'll be interesting how you tackle it. Best wishes and good luck.

[Harshitha @Harshit49678822]

Hey guys! Check out my very first blog on Mor1kx formal. Here is it's link

https://t.co/Woat6EL8l1

@stffrdhrn @gsoc @FossiFoundation

[PDVL @PDVLcc]

Open access papers till June for "The Fourth ACM SIGPLAN History of Programming Languages Conference, Co-Vital with PLDI 2012":

https://t.co/YyoPWLkyZ4

https://t.co/nrj0P1bWou

[PDVL @PDVLcc]

@cpitclaudel My Q wasn't precise enough, it was more about compile time from RHDL to C++. I'm a great fan of CA models. You can get even more performance using signal ordering, but that requires more compiler work:

https://t.co/rc6sp6qzwJ

[PDVL @PDVLcc]

Inspiring open accessible 2-pager available for LATTE ’21 (Workshop on Languages, Tools, and Techniques for Accelerator Design):

https://t.co/lLo6NvWw1A

[Arduissimo @arduissimo]

Trying to count electrons (or holes if I can detect some) as they fly by (almost) at the speed of light. Cycle accurate power consumption measurements of #RISCV cores. Oh boy, it’s not going to work. Wish me luck.

[PDVL @PDVLcc]

@unaimarcor @OlofKindgren @timonsku Sure, simulating black IP cores over the internet using Java websockets is sexy. I would assume that you can do that with verilator, SystemC, GHDL etc. I was just reminded of the time 20 years ago when we offered it on a prof base, but there wasn't the market for it at that time.

[Marcus Borba @marcusborba]

FREE 1020-page PDF eBook covers the #Mathematics of #DeepLearning

https://t.co/HltIoJvwT3 via @KirkDBorne

CC: @mvollmer1 @FmFrancoise @YvesMulkers @Fabriziobustama @jenstirrup @andi_staub

#AI #MachineLearning #BigData #Analytics #NeuralNetworks #DataScience #Algorithms #Books

[PDVL @PDVLcc]

@OlofKindgren @timonsku Awesome, reminds me of the time 20 years ago, when we automatically converted VHDL/Verilog to cycle accurate C models of the design and timing accurate JAVA testbenches, so IP providers can offer black model simulations. Maybe now it's time for that business model #edalize.

[PDVL @PDVLcc]

@dhdezr73 You inspired me to check my database for Hector again and I found this, also avail w/o paywall or registration. My question would be, has Hector changed in the last 12 years ? Cheers !

https://t.co/OwOKfaqz5m

[PDVL @PDVLcc]

@dhdezr73 I would do a lot for a Snps Hector presentation/lab. Unfort. there is little or no documentation/experience reports (a.k.a. limitation) available in the public.

[PDVL @PDVLcc]

@cpitclaudel

Alectryon looks really awesome. It works for the given recepies. But I tried it on the SWF first book, first file (Basic.v) and run into a lot of problems. Any hints to make it run ?

https://t.co/zFP1DprnzK

[ECOOP’26 Conference @ECOOPconf]

“Test-Case Reduction via Test-Case Generation: Insights From the Hypothesis Reducer” – @DRMacIver, @afd_icl. #ecoop20 #research #paper
➡️ https://t.co/reVZtHbUeY

[PDVL @PDVLcc]

The best free introductory course on formal verification I have ever seen: https://t.co/EFMuF4WXRU

[PDVL @PDVLcc]

@pulp_platform @ValtrixSystems Wondering how this compares to findings announced by a formal verification company, and if they used the same core version. #riscv

[WaveDrom @wavedrom]

Languages of the Future: Mandarin vs. JavaScript by @GoBomberbot https://t.co/MLbcgkYyMk

[The Rocq Prover @CoqLang]

The Coq Workshop 2020 will be held online on July 5-6. Everyone is welcome to join! Please see this Discourse post for more detail: https://t.co/Mn5xpfc7BM

[The Rocq Prover @CoqLang]

The REMS-@deep_spec workshop (part of @PLDI 2020) will be held online on June 15-16th:
https://t.co/hEOeKGP8uW
Registration is free but it closes on June 5th!