RISHIK RAM

Open source enthusiast || interested in Computer architecture (HW/SW) (noob)
|| Math Geek

Alum Undergrad: @IIT_BHILAI

[RISHIK RAM @ram_rishik]

And at the end everything is ai for ai ...

[Deepak Sharda @deeempak]

So we are at Semicon Taiwan
@ram_rishik @AksharVastarpar

[RISHIK RAM @ram_rishik]

@mnwsth 180nm try kar sakte h ?😋

[Rohan makes ASICs 🛠️ @always_ff_rohan]

And then the fun part started: debugging the actual chip. 😅

Full story
https://t.co/xH7caZZFL1

[RISHIK RAM @ram_rishik]

@vvolhejn comparing F1 with football 😂

[RISHIK RAM @ram_rishik]

First Tapeout Done and dusted

Started just as a thought now it has a physical form 🔥

@always_ff_rohan @skelegrow
@deeempak @AksharVastarpar

@FossiFoundation #openlane #librelane

[Akshar Vastarpara @AksharVastarpar]

Yes, credit goes to both of you, and to Praveen, Devang, Rishik, Deepak, and Tejas from the @Vicharak_In team.

Even on the very first attempt, all of you designed it like true masters.

[RISHIK RAM @ram_rishik]

@deeempak Waiting...

[RISHIK RAM @ram_rishik]

Frozen V2 in competition with taalas, etched

" Transformer architecture is done evolving,now model is new chip"

[NIK @ns123abc]

BREAKING: Google is developing a specialized inference chip because the compute crunch is so bad Google Cloud is turning down deals

New chip line: "Frozen v2" — descended from a Jeff Dean design that proposed etching Gemini weights directly into silicon

v2 freezes the architecture instead:

>gemini architecture hardwired into the chip
>10x tokens per WATT than newest TPUs for inference
>deployable as soon as 2028

DeepMind is betting that the transformer architecture is done evolving

The model is the chip now

[NIK @ns123abc]

BREAKING: Google is developing a specialized inference chip because the compute crunch is so bad Google Cloud is turning down deals

New chip line: "Frozen v2" — descended from a Jeff Dean design that proposed etching Gemini weights directly into silicon

v2 freezes the architecture instead:

>gemini architecture hardwired into the chip
>10x tokens per WATT than newest TPUs for inference
>deployable as soon as 2028

DeepMind is betting that the transformer architecture is done evolving

The model is the chip now

[Aryamman Bhatia @aryamman_bhatia]

India’s Semiconductor Mission needs tens of thousands of engineers with hands on semiconductor knowledge.

Most students (even EEs at elite universities) graduate without ever touching a silicon wafer.

This is the gap we’re attempting to bridge @hackerfabindia

Thanks Caleb!

[RISHIK RAM @ram_rishik]

@FGuzmanAI @karpathy Is this same as talos v2? That runs on cycloneV ?

[Aryamman Bhatia @aryamman_bhatia]

We fabricated and characterised our first semiconductor devices @hackerfabindia today- a PN junction(right) diode and a MOSCAP(left)- both using tools built entirely in house.

There’s obviously a lot of improvement to be made to our process, but it’s only upward from here!

[RISHIK RAM @ram_rishik]

@VulcanIgnis you can also check the grid of the fpga in bitstream by toggling/shifting them , it should be pretty easy to add in nextpnr but dont know if Renesas likes it

[Ken Shirriff @kenshirriff]

This pretty chip from 1981 helped connect an IBM mainframe to data-entry terminals. 1/14

[OpenHW Foundation @OpenHWFdn]

WOHA, big NEWS!!! another, awesome open source Hardware RTL project released by @Ainekk0 at the #OpenHW repository! And it is Apache 2.0 with some NICE #RISCV cores inside......
Plus real chips will be made, check out more! Come and collaborate!

@FelixCLC_ @rhatr

[RISHIK RAM @ram_rishik]

@b1shtream @hthieblot True , but there is work Life balance in that as well
It's just that whats your meaning of life in the given time

[Mehdi 麦迪⁠ @BetterCallMedhi]

chinese academy of sciences just dropped qimeng, an AI system that designs entire processor chips end to end from natural language spec to to physical layout, their first version qimeng-cpu-v1 produced a fully functional 32-bit RISC-V CPU in 5 hours with 4 milliongates, performance on par with intel's 1990s chips, version v2 already matches arm cortex a53 from the 2010s, the whole thing runs on a domain specific model that learns the graph structures of circuits the way GPT learns text

honestly i’ve been staring at this paper for an hour & i still can’t fully wrap my head around what it implies, this is what real sovereignty looks like, when an AI can design your chips you stop depending on TSMC EUV machines on synopsys cadence licenses on US export controls, every kid with a laptop becomes a potential chip architect, the bottleneck of semiconductor design that locked the industry into 5 companies worldwide just got broken open, the next decade of hardware will be designed by AI agents @ the country that owns those agents owns the future

think about what this means for everyone, custom chips for your medical implant designed in days, processors tuned for african languages built by ethiopian students, agricultural sensors optimized for malian soil sketched by farmers themselves, the entire 80y monopoly of SV over how computation gets shaped is about to dissolve into a planetary movement of garage chip designers,…

the same way the printing press took writing out of the monasteries this takes silicon out of the fabs, we are watching the MOST centralized industry on earth become the most distributed one & the window to participate is wide open rn

[RISHIK RAM @ram_rishik]

@blip_tm Axelera ai something to look at in europe front

[RISHIK RAM @ram_rishik]

@vibeonX69 Doesn't matter

[RISHIK RAM @ram_rishik]

Special mention
1. Simulating Partial Reconfiguration in cocotb via MultiProcess DPI Barriers

[RISHIK RAM @ram_rishik]

This year lineup for latch-up 2026 is super awesome

Few things to note*
1. Verilator 4 state support , uvm verification
2. OpenRoad and era of Ai agents

https://t.co/drGpynSkrw
#opensource #fpga #verilator #fossi
#asic